1. Field of the Invention
The present invention relates to a comparator unit for a flash A/D converter in which a bank of comparator units compare simultaneously an analog input voltage with equally spaced reference voltages, and an encoder ROM produces digital signals based on the comparator unit's outputs. More particularly, the present invention relates to a high speed comparator unit including a miller-effect reducer which reduces the miller-effect of latch transistors to increase comparison speed.
2. Description of the Prior Art
The flash A/D converter is the fastest of all converter systems. Conversion speed is limited by the speed of a comparator unit.
As shown in FIG. 1 (PRIOR ART), a conventional flash A/D converter comprises a plurality of comparator units 5 for simultaneously comparing an analog input voltage V.sub.in with equally spaced referenced voltages V.sub.ref. A voltage divider of resistors R.sub.n1, R.sub.n2, . . . R.sub.n2 m disposed between supply voltage V.sub.TOP and V.sub.BTM are connected to an inverting terminal (-) of each comparator CP.sub.1, CP.sub.2, . . . CP.sub.2 m, and an analog input voltage V.sub.in is connected to a noninverting terminal (+) of each comparator CP.sub.1, CP.sub.2, . . . CP.sub.2 m. Output terminals of the comparators CP.sub.1, CP.sub.2, . . . CP.sub.2 m are connected to encoder ROM 10 which converts the analog input voltage V.sub.in to a digital signal D.sub.1 . . . D.sub.m. Therefore, the comparators CP.sub.1-CP.sub.2 m compare the analog input voltage V.sub.in with the reference voltages V.sub.ref generated by the voltage divider and the encoder ROM 10 produces corresponding digital signals D.sub.1 . . . D.sub.m based upon these comparisons. As shown in FIG. 1, generally there are numerous comparators CP.sub.1, CP.sub.2, . . . CP.sub.2 m, and thus, numerous comparator units 5 are needed for a conventional flash A/D converter.
FIG. 2 (PRIOR ART) shows a circuit diagram of a conventional comparator unit 5 comprising clock driven transistor Q.sub.12 and Q.sub.13, transistors Q.sub.1-Q.sub.3, Q.sub.10 and Q.sub.11, latch transistor Q.sub.8 and Q.sub.9, and resistors R.sub.1 -R.sub.3 and R.sub.5.
When clock CK goes high, transistor Q.sub.13 turns on. If analog input voltage V.sub.in is higher than reference voltage V.sub.ref, a larger portion of current I.sub.2 flows through transistor Q.sub.10 than transistor Q.sub.11, thereby producing a larger voltage drop across resistor R.sub.2 than resistor R.sub.3. Accordingly, the voltage at the collector of transistor Q.sub.10 is lower than the voltage at the collector of transistor Q.sub.11. Since the voltage drop across resistor R.sub.3 is small (i.e., current I.sub.2 is smaller along the transistor Q.sub.11 side of the comparator), likewise the voltage drop across R.sub.1 is small because current I.sub.2 is small (VB1 is high, thus transistor Q.sub.2 is on). Thus, with a small current I.sub.2 at the collector of transistor Q.sub.2 (or enable terminal E.sub.n+1, which does not have current flowing from adjacent comparator CP.sub.i+1 along its corresponding transistor Q.sub.1 and enable terminal E.sub.n-1), output voltage V.sub.out at the emitter of transistor Q.sub.3 is a high level of V.sub.CC-V.sub.BE (Q.sub.3).
On the other hand, if analog input voltage V.sub.in is lower than reference voltage V.sub.ref, a larger portion of current I.sub.2 flows through transistor Q.sub.11 than transistor Q.sub.10, thereby producing a larger voltage drop across resistor R.sub.3 than resistor R.sub.2. Accordingly, the voltage at the collector of transistor Q.sub.10 is higher than the voltage at the collector of transistor Q.sub.11. Since the voltage drop across resistor R.sub.3 is large (i.e., current I.sub.2 is larger along the transistor Q.sub.11 side of the comparator), likewise the voltage drop across R.sub.1 is larger because current I.sub.2 is larger (VB1 is high, thus transistor Q.sub.2 is on). Thus, with a larger current I.sub.2 at the collector of transistor Q.sub.2 (or enable terminal E.sub.n+1), output voltage V.sub.out at the emitter of transistor Q.sub.3 is a low level of V.sub.CC -I.sub.2 .times.R.sub.1 -V.sub.BE (Q.sub.3).
When CK goes high, transistor Q.sub.12 turns on thereby allowing current I.sub.2 to flow through latch transistors Q.sub.8 and Q.sub.9. Since the collector voltages of transistors Q.sub.10 and Q.sub.11 are connected to the bases of latch transistors Q.sub.8 and Q.sub.9, during latching the collector voltages of transistors Q.sub.8 -Q.sub.11 maintain their pre-state voltages, thus maintaining the voltage difference between the collectors of latch transistors Q .sub.8 and Q.sub.9. If analog input voltage V.sub.in is larger than reference voltage V.sub.ref, current I.sub.2 flows through transistor Q.sub.12, latch transistor Q.sub.9, resistor R.sub.2, and transistor Q.sub.1 to enable terminal E.sub.n-1 and decreases the collector voltage of latch transistor Q.sub.9 by I.sub.2 .times.R.sub.2 lower than latch transistor Q.sub.8. On the other hand, if analog input voltage V.sub.in is smaller than reference voltage V.sub.ref, current I.sub.2 flows through transistor Q.sub.12, latch transistor Q.sub.8, resistor R.sub.3, and transistor Q.sub.2 and decreases the collector voltage of latch transistor Q.sub.8 by I.sub.2 .times.R.sub.3 lower than latch transistor Q.sub.8.
By this latching operation, when analog input voltage V.sub.in is larger than reference voltage V.sub.ref of comparator CP.sub.i and smaller than reference voltage V.sub.ref of comparator CP.sub.i+1, only comparator CP.sub.i provides a high level output voltage V.sub.out while the other comparators produce low level output voltages.
However, in a conventional comparator unit, resistors R.sub.2 and R.sub.3 are connected between the emitters of transistors Q.sub.1 and Q.sub.2 and the collectors of latch transistors Q.sub.8 and Q.sub.9 causing a loop (for examples, the loop for latch transistor Q.sub.9 comprises the collector of latch transistor Q.sub.9, resistor R.sub.2, the emitter of transistor Q.sub.1, the bases of transistors Q.sub.1 and Q.sub.2, the emitter of transistor Q.sub.2, resistor R.sub.3, the base of latch transistor Q.sub.9) to have a gain which increases the miller-capacitance between the collectors and bases of latch transistor Q.sub.8 and Q.sub.9, thus lowering the speed of the comparator unit 5.